[XEN][POWERPC] Whitespace.
authorhollisb@localhost <hollisb@localhost>
Mon, 18 Sep 2006 18:21:39 +0000 (13:21 -0500)
committerhollisb@localhost <hollisb@localhost>
Mon, 18 Sep 2006 18:21:39 +0000 (13:21 -0500)
Signed-off-by: Hollis Blanchard <hollisb@us.ibm.com>
xen/arch/powerpc/powerpc64/ppc970.c
xen/include/asm-powerpc/cache.h
xen/include/asm-powerpc/page.h

index db116c5416cfc9d0154f27fb907427a4b0aa91a4..11fd303001ec09c20968979a46d4db35eba22c15 100644 (file)
 #undef SERIALIZE
 
 struct cpu_caches cpu_caches = {
-       .dline_size = 0x80,
-       .log_dline_size = 7,
+    .dline_size = 0x80,
+    .log_dline_size = 7,
     .dlines_per_page = PAGE_SIZE >> 7,
-       .iline_size = 0x80,
-       .log_iline_size = 7,
+    .iline_size = 0x80,
+    .log_iline_size = 7,
     .ilines_per_page = PAGE_SIZE >> 7,
 };
 
index 7f5a89a0b0f7cff09e84f8db1ee09b1aaa632acb..04f86c64f73eb0f3a20566d268658c7445b20afe 100644 (file)
@@ -60,14 +60,14 @@ static __inline__ void synchronize_caches(ulong start, size_t len)
 #define __read_mostly
 
 struct cpu_caches {
-       u32     dsize;                  /* L1 d-cache size */
-       u32     dline_size;             /* L1 d-cache line size */
-       u32     log_dline_size;
-       u32     dlines_per_page;
-       u32     isize;                  /* L1 i-cache size */
-       u32     iline_size;             /* L1 i-cache line size */
-       u32     log_iline_size;
-       u32     ilines_per_page;
+    u32 dsize;          /* L1 d-cache size */
+    u32 dline_size;     /* L1 d-cache line size */
+    u32 log_dline_size;
+    u32 dlines_per_page;
+    u32 isize;          /* L1 i-cache size */
+    u32 iline_size;     /* L1 i-cache line size */
+    u32 log_iline_size;
+    u32 ilines_per_page;
 };
 extern struct cpu_caches cpu_caches;
 #endif
index f98d78d363c67fc6ad06738bdae0143be7b564e0..f3fbaeb1ad1e5f1e441c7352e5963ab5b9a52310 100644 (file)
@@ -73,19 +73,19 @@ typedef struct { unsigned long l1_lo; } l1_pgentry_t;
 
 static __inline__ void clear_page(void *addr)
 {
-       unsigned long lines, line_size;
+    unsigned long lines, line_size;
 
-       line_size = cpu_caches.dline_size;
-       lines = cpu_caches.dlines_per_page;
+    line_size = cpu_caches.dline_size;
+    lines = cpu_caches.dlines_per_page;
 
-       __asm__ __volatile__(
-       "mtctr  %1      # clear_page\n\
-1:      dcbz   0,%0\n\
-       add     %0,%0,%3\n\
-       bdnz+   1b"
+    __asm__ __volatile__(
+    "mtctr  %1      # clear_page\n\
+1:  dcbz    0,%0\n\
+    add     %0,%0,%3\n\
+    bdnz+   1b"
     : "=r" (addr)
     : "r" (lines), "0" (addr), "r" (line_size)
-       : "ctr", "memory");
+    : "ctr", "memory");
 }
 
 extern void copy_page(void *dp, void *sp);